1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a test mode signal generation device which generates a test mode signal from address signals. 2. Related Art
In order to guarantee the reliability of a semiconductor memory apparatus, various tests are performed on the semiconductor memory apparatus during its manufacture or, before end products are put on the market. Since fields for testing the performance of a semiconductor memory apparatus are diverse, a plurality of test modes are established, and tests of the semiconductor memory apparatus are performed based on pre-established test modes. In general, a semiconductor memory apparatus generates test mode signals for entry to specified test modes by combining address signals.
FIG. 1 is a block diagram schematically illustrating the configuration of a conventional test mode signal generation device. Referring to FIG. 1, a conventional test mode signal generation device includes a control unit 10, an address decoder 20, and a test mode signal generation unit 30. The control unit 10 receives address signals
MREG<0:6>, a normal MRS signal NMRSP, a test MRS signal TMRSP, and a power-up signal PWRUP. The control unit 10 generates transmission address signals TMREG<0:6> according to the address signals MREG<0:6> when the test MRS signal TMRSP is enabled, and generates a reset signal TRSTPB using the normal MRS signal NMRSP and the power-up signal PWRUP. The address decoder 20 generates test address signals TRG01<0:3>, TRG234<0:7> and TRG56<0:3> by decoding the transmission address signals TMREG<0:6> inputted through the control unit 10. The test mode signal generation unit 30 receives the test address signals TRG01<0:3>, TRG234<0:7> and TRG56<0:3> and generates test mode signals TM. The test mode signal generation unit 30 has a plurality of signal generation sections 31, 32, 33 and 34, and generates a plurality of different test mode signals TM depending on the number of possible combinations of the test address signals TRG01<0:3>, TRG234<0:7>and TRG56<0:3>.
FIG. 2 is diagram illustrating a state in which the test mode signal generation device in FIG. 1 is disposed in a semiconductor apparatus. Referring to FIG. 2, a semiconductor apparatus includes 8 memory banks BANK0 through BANK7, and the test mode signal generation device in FIG. 1 is disposed in a peripheral area between the memory banks BANK0 through BANK7. The test mode signals TM generated by the test mode signal generation device are directly transmitted to logic circuits L0 through Lm and Lm+1 through Ln, which require the test mode signals TM, through global lines. In the case where the test mode signal generation device employs 7 address signals as shown in FIG. 1, 128 total test mode signals can be generated. Accordingly, in the case where the test mode signals are directly transmitted through the global lines, the number of global lines is necessarily 128. If such a large number of global lines are disposed in the peripheral area in which a number of circuits are provided for the normal operation of the semiconductor memory apparatus, wiring is complicated, and a layout margin decreases. Also, in the conventional test mode signal generation device, a limited number of test mode signals are generated according to a limited number of address signals.